2. axvm
3. 1. Overview
4. 2. Core Architecture
5. 1. 2.1. Virtual Machine Implementation
   2. 2.2. Virtual CPU Architecture
   3. 2.3. Hardware Abstraction Layer
6. 3. Configuration System
7. 4. Dependencies and Integration
8. 5. Development Guide
9. 1. 5.1. Build and Testing
   2. 5.2. License and Legal
11. axvisor
12. 6. Overview
13. 7. Architecture
14. 1. 7.1. System Components
    2. 7.2. VM Management
    3. 7.3. Hardware Abstraction Layer
    4. 7.4. Memory Management
15. 8. Configuration
16. 1. 8.1. VM Configuration
    2. 8.2. Platform-Specific Configuration
17. 9. Building and Running
18. 1. 9.1. Guest VMs
    2. 9.2. Development Environment
19. 10. Technical Reference
20. 1. 10.1. VMM Implementation
    2. 10.2. VCPU Management
    3. 10.3. Timer Subsystem
21. 11. Contributing
22. 1. 11.1. Testing Infrastructure
    2. 11.2. CI/CD Pipeline
24. axdevice_crates
25. 12. Overview
26. 1. 12.1. Project Structure
27. 13. Core Architecture
28. 1. 13.1. BaseDeviceOps Trait
    2. 13.2. Device Type System
    3. 13.3. Address Space Management
29. 14. Dependencies and Integration
30. 1. 14.1. ArceOS Integration
31. 15. Development Guide
32. 1. 15.1. Build System and CI
    2. 15.2. Implementing New Devices
34. arm_vcpu
35. 16. Overview
36. 1. 16.1. System Architecture
    2. 16.2. Dependencies and Build System
37. 17. Virtual CPU Management
38. 1. 17.1. VCPU Lifecycle and Operations
    2. 17.2. Per-CPU State Management
39. 18. Context Switching and State Management
40. 1. 18.1. TrapFrame and System Registers
41. 19. Exception Handling System
42. 1. 19.1. Assembly Exception Vectors
    2. 19.2. Exception Analysis and Utilities
    3. 19.3. High-Level Exception Handling
43. 20. System Integration
44. 1. 20.1. Secure Monitor Interface
    2. 20.2. Hardware Abstraction and Platform Support
46. axvcpu
47. 21. Overview
48. 22. Core VCPU Management
49. 1. 22.1. VCPU State Machine and Lifecycle
    2. 22.2. Architecture Abstraction Layer
50. 23. Exit Handling System
51. 1. 23.1. Exit Reasons and Categories
    2. 23.2. Memory Access and I/O Operations
52. 24. Implementation Details
53. 1. 24.1. Per-CPU Virtualization State
    2. 24.2. Hardware Abstraction Layer
54. 25. Development and Build System
55. 1. 25.1. Dependencies and Integration
    2. 25.2. Testing and Continuous Integration
56. 26. Licensing and Legal
58. axaddrspace
59. 27. Overview
60. 28. Core Architecture
61. 1. 28.1. Address Types and Spaces
    2. 28.2. Address Space Management
    3. 28.3. Hardware Abstraction Layer
62. 29. Nested Page Tables
63. 1. 29.1. Architecture Selection
    2. 29.2. AArch64 Implementation
    3. 29.3. x86_64 Implementation
    4. 29.4. RISC-V Implementation
64. 30. Memory Mapping Backends
65. 1. 30.1. Linear Backend
    2. 30.2. Allocation Backend
66. 31. Device Support
67. 32. Development Guide
69. riscv_vcpu
70. 33. Overview
71. 34. Core VCPU Implementation
72. 1. 34.1. VCPU Lifecycle and Management
    2. 34.2. SBI Interface and Hypercalls
    3. 34.3. VM Exit Processing
73. 35. System Architecture
74. 1. 35.1. Per-CPU Management
    2. 35.2. Hardware Detection
    3. 35.3. Register Management
75. 36. Low-Level Implementation
76. 1. 36.1. Trap Handler Implementation
    2. 36.2. CSR Definitions and Hardware Registers
    3. 36.3. System Constants and Trap Definitions
77. 37. Development and Tooling
79. axdevice
80. 38. Overview
81. 39. System Architecture
82. 40. Core Components
83. 1. 40.1. Configuration Management
    2. 40.2. Device Emulation
84. 41. ArceOS Ecosystem Integration
85. 42. Development Guide
87. x86_vcpu
88. 43. Overview
89. 44. VMX Virtualization Engine
90. 1. 44.1. Virtual CPU Management
    2. 44.2. VMX Data Structures
    3. 44.3. VMCS Field Management
    4. 44.4. Per-CPU VMX State
91. 45. Memory Management
92. 1. 45.1. Physical Frame Management
    2. 45.2. Extended Page Tables and Guest Memory
93. 46. Supporting Systems
94. 1. 46.1. Register Management
    2. 46.2. Model-Specific Register Access
    3. 46.3. VMX Definitions and Types
    4. 46.4. VMX Instructions
95. 47. Development and Configuration
96. 1. 47.1. Project Configuration
    2. 47.2. Build System and CI
98. arm_vgic
99. 48. Overview
100. 49. System Architecture
101. 50. Core Components
102. 1. 50.1. Virtual GIC Controller (Vgic)
     2. 50.2. CPU Interface (Vgicc)
     3. 50.3. Device Operations Interface
     4. 50.4. Constants and Register Layout
103. 51. Dependencies and Integration
104. 1. 51.1. Dependency Analysis
     2. 51.2. Build Configuration
106. x86_vlapic
107. 52. Overview
108. 53. Core Architecture
109. 1. 53.1. EmulatedLocalApic Device Interface
     2. 53.2. Virtual Register Management
     3. 53.3. Register Address Translation
110. 54. Register System
111. 1. 54.1. Register Constants and Offsets
     2. 54.2. Local Vector Table (LVT)
     3. 1. 54.2.1. Timer LVT Register
        2. 54.2.2. External Interrupt Pin Registers
        3. 54.2.3. System Monitoring LVT Registers
        4. 54.2.4. Error Handling LVT Registers
     4. 54.3. Control and Status Registers
112. 55. Development and Project Management
114. arm_gicv2
115. 56. Overview
116. 57. Core Architecture
117. 1. 57.1. GIC Distributor Component
     2. 57.2. CPU Interface Component
     3. 57.3. Interrupt Processing Pipeline
118. 58. Interrupt Types and Management
119. 1. 58.1. Interrupt Classification System
     2. 58.2. Software Generated Interrupts
120. 59. Register Interface
121. 1. 59.1. Register Module Organization
     2. 59.2. GICD_SGIR Register Details
122. 60. Development and Integration
123. 1. 60.1. Crate Configuration and Dependencies
     2. 60.2. Build System and Development Workflow